Note on the value of margin in CMOS scaling

I discovered a very illustrative slide on the potential of exploiting the design margins in CMOS technology, especially for the deeply scaled CMOS.

ref: Designers’ guide to maintain Moore’s law – by Kahng UCSD, 2012

CMOS non-idealities are produced due to physical constraints. Therefore, the time-0 variablity (wafer-to-wafer, die-to-die, within-die), as well as the time-dependent aging (NBTI/PBTI, HCI, EM), result to randomized circuit behavior. The variability enlarges, as circuit scaling-down to smaller feature size.

Variability increases as CMOS scaling

However, the high-k metal gate presented in TSMC 28nm rescues this margin, since the the channel is then less dopanted. And thus variability DOES NOT increase when scaled to 28nm.

Worth-noting that Typical-Typical delay of TSMC28 hkmg is also ~2.3 faster than Slow-Slow case, including the effects of 10% voltage drop and 0C vs. 80C in temperature.

The effect on variability of 16nm FinFet is still unknown, which is driven into two directions by two counter-factors: 1) 16nm is indeed smaller, and hence it should become worse; 2) yet the variabilty should improve due to: almost no channel dopant is required, since the gate contours the channel, and hence controls it better.

The adaptive controlling method can exploit the margin:

Adaptively control the supply to shave margin